This disclosure relates to finFET devices and to methods for manufacturing the same.
Metal-Oxide-Semiconductor field effect transistor (MOSFET) technology is the dominant electronic device technology in use today. Performance enhancement and cost reduction between generations of integrated circuits (ICs) is generally achieved by reducing the size of transistors in the ICs, resulting in an enhancement in transistor speed and increasing integrated transistor area density. This is generally referred to as transistor “scaling”.
Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as more than one million transistors and even several billion transistors that cooperate to perform various functions for an electronic component. The transistors are generally complementary metal oxide semiconductor field effect transistors (CMOSFETs) that include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material or high-k material. Generally, the gate conductor can be a metal, a polysilicon, or polysilicon/germanium (SixGe(1-x)) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
In semiconductor-on-insulator (SOI) semiconductor-type devices, transistors such as MOSFETs, are built on the top surface of a SOI substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the SOI thickness of the transistor is scaled down to achieve superior short-channel performance.
As MOSFETs are scaled to channel lengths below 100 nm, conventional MOSFETs suffer from several problems. In particular, interactions between the source and drain of the MOSFET degrade the ability of the gate to control whether the device is on or off. This phenomenon is called the “short-channel effect” or SCE.
In order to reduce SCE, double-gate MOSFET structures have been designed. In a double-gated MOSFET, a second gate is disposed in the device between the source and the drain such that there is a gate on either side of a channel that connects the source and the drain. This allows gate control of the channel from both sides, reducing SCE. Additionally, when the device is turned on using both gates, two conduction (“inversion”) layers are formed, allowing for more current flow. An extension of the double-gate concept is the “surround-gate” or “wraparound-gate” concept, where the gate is placed such that it completely or almost-completely surrounds the channel, providing better gate control.
As one type of double gate device, finFET devices have received significant attention because of their advantages related to high drive current, high immunity to short channel effects, and relative easiness of manufacture.
However, as the miniaturization of semiconductor devices proceeds, patterning narrow, dense active regions has become more challenging. For example, conventional lithographic tools are unable to accurately and precisely define active regions as structures or features with dimensions below 100 nm or 50 nm. It is therefore desirable to have a manufacturing process that affords the patterning of narrow, dense, active regions that can be used for fabricating a finFET device. It is also desirable that the manufacturing process be compatible with existing MOSFET fabrication processes.